Dual Column, Replica Bitline Delay Technique Using Stochastic Current Processing for a Process Variation Tolerant, Low Power SRAM

SRAM (Static Random Access Memory) design has become the critical and important block in processing ICs with the highest bandwidth power rationed memories taking the business lead. As industry attempts to maintain Moore's law by shrinking the device size, we are facing greater issues with the variability due to random doping fluctuation in devices. This variation compels engineers to design for worst case conditions which leads to inefficient memory model, which make it difficult to stand in the business race. However, a smart design can lead to less variation and “exact” memory parametric prediction to achieve high performance, low power and maximum yield designs. Since, random variation today is more dominant, we consider the application of the central limit theorem to control memory read timing across PVT (Process Voltage Temperature) corners. A statistical read timing is developed for a SRAM memory bank. In the thesis two dummy columns, each at extreme end of the memory bank, are used to implement the statistical memory bank model. By combining Monte-Carlo analysis using cadence virtuoso, and PDK data for the CMOS process (IBM 7RF), an analytically memory timing model is verified. Our major goal is to improve yield across all memory banks in all die across all the wafers; slow-slow (SS), typical-typical (TT) and fast-fast (FF).A smart stochastic/statistical approach is used in the thesis to predict exact parametric yield parameters with less variation to design accurate memory system which gives high performance, low power and maximum yield across all PVT corners to keep you ahead in the memory business. The memory design is compared to the conventional self-timed replica architecture using coefficient of variance of a reference current generated using dummy column. The proposed architecture was able to achieve 62 percent across the process improved accuracy in reference current and sense amplifier firing variation. Proposed architecture looks promising for future node technologies where statistical variability and its impact in subthreshold region is more dominant.Electrical Engineerin