Power-speed trade-off in parallel prefix circuits.

Optimizing area and speed in parallel prefix circuits have been considered important for long time. The issue of power consumption in these circuits, however, has not been addressed. This dissertation presents a comparative study of different parallel prefix circuits from the point of view of power-speed trade-off. The power consumption and the power-delay product of seven parallel prefix circuits were compared. A linear output capacitance assumption, combined with PSpice simulations, is used to investigate the power consumption in the circuits. The degrees of freedom studied include different parallel prefix algorithms and voltage scaling. The results show that the use of the linear output capacitance assumption provides results that are consistent with those obtained using PSpice simulations. Because of the size-depth trade-off characteristic of prefix circuits, the results also show that parallelism of prefix circuits at a certain level coupled with the use of low supply voltage can be used to reduce the power-delay product to attain a desired throughput beyond the minimum possible. The study enables us to understand the power consumption behavior of prefix circuits, and to pick the suitable prefix circuit for the acceptable power consumption in the prefix with a given throughput. Circuit designers can then choose the best prefix circuit for a particular application