Hardware and software for WINC2R cognitive radio platform

Emerging wireless technologies and standards require inter-operability between devices whose infrastructure has been built using different radio access technologies and which operate in different spectrum bands. In this thesis, we study the feasibility of building such a multi-protocol platform - the WINC2R platform. WINC2R is a platform for cognitive radio applications that has the agility needed for the per-packet protocol adaptation across the protocol layers and flexible enough to support the future evolution of the wireless communication protocols. The WINC2R platform concept is based on the generic processing engines that each handles processing for the computationally intensive physical and MAC layer functions. They are augmented with a software programmable processor that can handle the differences between the standards and future changes of those functions. The microprocessor environment forms one of the processing engines and can support additional functions with a suffciently low complexity without sacrificing the performance in terms of latency and throughput. The WINC2R architecture satisfies the requirements of low latency and fast context switching as required by the multi-layer protocol processing. The WINC2R system consists of three distinct layers: the data layer, the interconnection layer and the control layer. The data layer handles all the processing engines and its functionalities. Flexibility and programmability is achieved through the interconnections between the processing engines. In this thesis, we work with the control layer which consists of the underlying hardware that supports the control functions like handling interrupts from the processing engines, synchronizing the tasks, etc. The underlying hardware is customizable for system connectivity, Digital Signal Processing (DSP), and data processing applications which are required for the physical layer. The control functions are used to maintain the WINC2R system integrity and manage the wireless protocols. They also enable communication among the functional modules themselves. We examine the overall system and task processing flow. The interconnection layer deals with interconnecting the processing engines together which is handled by the Unit Control Module (UCM). At the heart of every processing engine lies the UCM that assigns and schedules tasks to and from the functional blocks with the help of a centralized data structure. It is in charge of scheduling the tasks to the module that it is associated with, assigning the task, monitoring the task completion, and communicating with the other modules in the system for task sequencing. The UCM is analyzed, and we study the feasibility of various tasks occurring in time. We propose a timeline for the occurrence of data and control tasks in different scenarios and study the feasibility of these scenarios.M.S.Includes bibliographical references (p. 59-60)