Circuit variation is one of the biggest problems to overcome if Moore\u27s Law is to continue. It is no longer possible to maintain an abstraction of identical devices without huge yield losses, performance penalties, and energy costs. Current techniques such as margining and grade binning are used to deal with this problem. However, they tend to be conservative, offering limited solutions that will not scale as variation increases. Conventional circuits use limited tests and statistical models to determine the margining and binning required to counteract variation. If the limited tests fail, the whole chip is discarded. On the other hand, reconfigurable circuits, such as FPGAs, can use more fine-grained, aggressive techniques that carefull...
Each new generation of FPGAs features smaller transistor sizes and more densely arranged features. T...
textTiming analysis is a key sign-off step in the design of today's chips, but technology scaling in...
This thesis proposes optimisation methods for improving the timing performance of digital circuits ...
Circuit variation is one of the biggest problems to overcome if Moore\u27s Law is to continue. It is...
Circuit variation is one of the biggest problems to overcome if Moore\u27s Law is to continue. It is...
Timing Extraction identifies the delay of fine-grained components within an FPGA. From these compute...
Timing Extraction identifies the delay of fine-grained components within an FPGA. From these compute...
This thesis examines new timing measurement methods for self delay characterisation of Field-Program...
Circuits implemented in FPGAs have delays that are dom-inated by its programmable interconnect. This...
As integrated circuits are scaled down it becomes dif-ficult to maintain uniformity in process param...
Reliability, power consumption and timing performance are key concerns for today's integrated circui...
This thesis examines new timing measurement methods for self delay characterisation of Field-Program...
Field Programmable Gate Arrays (FPGAs) are a widely used platform for hardware acceleration and digi...
This paper studies the difficulty of predicting interconnect delay in an industrial setting. Fifty i...
Both random and systematic within-die process variations (PV) are growing more severe with shrinking...
Each new generation of FPGAs features smaller transistor sizes and more densely arranged features. T...
textTiming analysis is a key sign-off step in the design of today's chips, but technology scaling in...
This thesis proposes optimisation methods for improving the timing performance of digital circuits ...
Circuit variation is one of the biggest problems to overcome if Moore\u27s Law is to continue. It is...
Circuit variation is one of the biggest problems to overcome if Moore\u27s Law is to continue. It is...
Timing Extraction identifies the delay of fine-grained components within an FPGA. From these compute...
Timing Extraction identifies the delay of fine-grained components within an FPGA. From these compute...
This thesis examines new timing measurement methods for self delay characterisation of Field-Program...
Circuits implemented in FPGAs have delays that are dom-inated by its programmable interconnect. This...
As integrated circuits are scaled down it becomes dif-ficult to maintain uniformity in process param...
Reliability, power consumption and timing performance are key concerns for today's integrated circui...
This thesis examines new timing measurement methods for self delay characterisation of Field-Program...
Field Programmable Gate Arrays (FPGAs) are a widely used platform for hardware acceleration and digi...
This paper studies the difficulty of predicting interconnect delay in an industrial setting. Fifty i...
Both random and systematic within-die process variations (PV) are growing more severe with shrinking...
Each new generation of FPGAs features smaller transistor sizes and more densely arranged features. T...
textTiming analysis is a key sign-off step in the design of today's chips, but technology scaling in...
This thesis proposes optimisation methods for improving the timing performance of digital circuits ...