Writing correct synchronization is one of the main difficulties of multithreaded programming. Incorrect synchronization causes many subtle concurrency errors such as data races and atomicity violations. Previous work has proposed stronger memory consistency models to rule out certain classes of concurrency bugs. However, these approaches are limited by a program’s original (and possibly incorrect) synchronization. In this work, we provide stronger guarantees than previous memory consistency models by punctuating atomicity only at ordering constructs like barriers, but not at lock operations. We describe the Ordering-free Regions for Consistency and Atomicity (ORCA) system which enforces atomicity at the granularity of ordering-free regions ...
Transactional memory has great potential for simplifying multithreaded programming by allowing progr...
technical reportThis paper explores the practicality of conducting program analysis for multithread...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...
Writing correct synchronization is one of the main difficulties of multithreaded programming. Incorr...
Correctly synchronizing multithreaded programs is challenging, and errors can lead to program failur...
Correctly synchronizing multithreaded programs is challenging, and errors can lead to program failur...
Store misses cause significant delays in shared-memory multiprocessors because of limited store buff...
AbstractEnsuring the correctness of multithreaded programs is difficult, due to the potential for un...
Multicore machines have become pervasive and, as a result, parallel programming has received renewe...
Writing shared-memory parallel programs is an error-prone process. Atomicity violations are especial...
Writing correct shared-memory concurrent programs is hard. Not only must a programmer reason about ...
Building correct and efficient concurrent algorithms is known to be a difficult problem of fundamental...
AbstractWe extend the notion of Store Atomicity [Arvind and Jan-Willem Maessen. Memory model = instr...
With the introduction of multi-core CPUs, multi-threaded programming is becoming significantly more ...
As computing hardware moves to multi-core systems, future software needs to be parallelized in order...
Transactional memory has great potential for simplifying multithreaded programming by allowing progr...
technical reportThis paper explores the practicality of conducting program analysis for multithread...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...
Writing correct synchronization is one of the main difficulties of multithreaded programming. Incorr...
Correctly synchronizing multithreaded programs is challenging, and errors can lead to program failur...
Correctly synchronizing multithreaded programs is challenging, and errors can lead to program failur...
Store misses cause significant delays in shared-memory multiprocessors because of limited store buff...
AbstractEnsuring the correctness of multithreaded programs is difficult, due to the potential for un...
Multicore machines have become pervasive and, as a result, parallel programming has received renewe...
Writing shared-memory parallel programs is an error-prone process. Atomicity violations are especial...
Writing correct shared-memory concurrent programs is hard. Not only must a programmer reason about ...
Building correct and efficient concurrent algorithms is known to be a difficult problem of fundamental...
AbstractWe extend the notion of Store Atomicity [Arvind and Jan-Willem Maessen. Memory model = instr...
With the introduction of multi-core CPUs, multi-threaded programming is becoming significantly more ...
As computing hardware moves to multi-core systems, future software needs to be parallelized in order...
Transactional memory has great potential for simplifying multithreaded programming by allowing progr...
technical reportThis paper explores the practicality of conducting program analysis for multithread...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...