Comparing strategies to bound the latencies of the MPPA Network-on-Chipi (Extended version)

The Kalray MPPA2-256 processor integrates 256 processing cores and 32 management cores on a chip. Theses cores are grouped into clusters, and clusters are connected by a high-performance network on chip (NoC). This NoC provides hardware mechanisms (ingress traffic limiters) that can be configured to offer service guarantees. This paper introduces a network calculus formulation for configuring the NoC traffic limiters, in order to guarantee upper bounds on the NoC traversal latencies. This network calculus formulation accounts for the traffic shaping performed by the NoC links, and can be solved using linear programming. This paper then shows how existing network calculus approaches (the Separated Flow Analysis-SFA ; the Total Flow Analysis-TFA ; the Linear Programming approach-LP) can be adapted to analyze this NoC. The latency bounds obtained are then compared on three case studies: two small configurations coming from previous studies, and one realistic configuration with 128 or 256 flows. From theses cases studies, it appears that modeling the shaping introduced by NoC links is of major importance to get accurate bounds. And when packets are of constant size, the Total Flow Analysis gives, on average, bounds 20%-25% smaller than all other methods, since its is the only able, up to now, to accurately and efficiently model these aspects