Understanding Memory Access Behavior for Heterogeneous Memory Systems

Present day manufacturers have invented different memory technologies with distinct bandwidth, energy and cost trade-offs. Systems with such heterogeneous memory technologies can only achieve the best performance and power characteristics by appropriately partitioning process data on OS pages and placing OS pages in the right memory areas. To achieve effective data partitioning and placement we need to first understand how programs access memory and how those patterns change at various stages (phases) of program execution. The goal of this work is to build a framework, design experiments and conduct analysis to understand overall memory usage patterns across many programs. We use Intel’s Pin dynamic binary translation and instrumentation system for this work. Our Pin based framework instruments programs at run-time to collect data regarding memory allocations, de-allocations, reads and writes, which we then analyze using our specialized scripts. We collect and analyze information including page access counts, hot page ratio, memory read and write access patterns and how that varies in different program phases. We also analyze the similarities regarding memory behavior between distinct phases during program execution. We also study memory behavior both with cache and without cache to understand how caches affect the memory access behavior