Advanced Encoding Schemes and their Hardware Implementation for Brain Inspired Computing

According to Moore’s law the number of transistors per square inch double every two years. Scaling down technology reduces size and cost however, also increases the number of problems. Our current computers using Von-Neumann architectures are seeing progressive difficulties not only due to scaling down the technology but also due to grid-lock situation in its architecture. As a solution to this, scientists came up architectures whose function resembles that of the brain. They called these brains inspired architectures, neuromorphic computers. The building block of the brain is the neuron which encodes, decodes and processes the data. The neuron is known to accept sensory information and converts this information into a spike train. This spike train is encoded by the neuron using different ways depending on the situation. Rate encoding, temporal encoding, population encoding, sparse encoding and rate-order encoding are a few encoding schemes said to be used by the neuron. These different neural encoding schemes are discussed as the primary focus of the thesis. A comparison between these different schemes is also provided for better understanding, thus helping in the design of an efficient neuromorphic computer. This thesis also focusses on hardware implementation of a neuron. Leaky Fire and Integrate neuron model has been used in this work which uses spike-time dependent encoding. Different neuron models are discussed with a comparison as to which model is effective under which circumstances. The electronic neuron model was implemented using 180nm CMOS Technology using Global Foundries PDK libraries. Simulation results for the neuron are presented for different inputs and different excitation currents. These results show the successful encoding of sensory information into a spike train