A Robust Low Power Static Random Access Memory Cell Design

Stability of a Static Random Access Memory (SRAM) cell is an important factor when considering an SRAM cell for any application. The Static Noise Margin (SNM) of a cell, which determines the stability, varies under different operating conditions. Based on the performance of three existing SRAM cell designs, 6T, 8T and 10T, a 10 Transistor SRAM cell is proposed which has good stability and has the advantage of reduced read power when compared to 6T and 8T SRAM cells. The proposed 10T SRAM cell has a single-ended read circuit which improves SNM over the 6T cell. The proposed 10T cell doesn\u27t require a pre-charge circuit and this in-turn improves read power and also reduces the read time since there is no need to pre-charge the bit-line before reading it. The Read SNM and Hold SNM of the proposed cell at a VDD of 1V and at 25°C is 254mV. The measured RSNM, HSNM and Write SNM at temperatures 0°C, 40°C, 80°C and 120°C and also at supply voltages 1V, 0.8V and 0.6V show the design is robust. The Write SNM of the proposed cell at a VDD of 1V and Pull-up Ratio of 1 is 275mV. Finally, a 32-byte memory array is built using the proposed 10T SRAM cell and the read, write times are 149ps and 21.6ps, respectively. The average power consumed by the 32-byte array over a 12ns period is 13.8uW. All the designs are done in the 32nm FinFET technology