FET and VDP Stress Sensors for Experimental Characterization of Die Stress in Electronic Packages

Structural reliability of integrated circuit chips in electronic packages continues to be a major concern due to ever increasing die size, circuit densities, power dissipation, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. Resistive rosettes on (100) silicon can be used to measure as many as four components of the six-component stress state whereas advanced test chips based upon (111) silicon can measure the complete stress state. Classic resistor rosettes suffer from reduced sensitivity due to high doping levels, and they measure values of the die surface stress averaged over a relatively large area. Also, they cannot be used a high temperatures (e.g. during packaging processes such as encapsulation) because they have rather large junction areas which leads to large leakage currents. In this paper, the researchers present several new sensor capabilities which offer several exciting advantages over conventional resistor sensors. In particular, advanced stress sensors based upon the piezoresistive response of field-effect transistors (FETs) and van der Pauw (VDP) test structures are presented. These sensors are demonstrated to provide improved sensitivity and highly localized measurement of stress sensitivity over an areas of approximately 1mm(2). The high temperature performance of these sensors is also demonstrated, proving that they are excellent candidates for in-situ measurement of stresses induced by manufacturing (packaging) processes such as encapsulation of plastic packages or flip chip packages