Mixed-Signal Implementation of Low-Density Parity-Check Decoder

The receiver side of many communication systems incorporates an error-correction decoder to achieve good bit-error rate (BER) performance. While good BER is a metric of reliable communication, high throughput and energy-efficiency are also desired. Low-density parity-check (LDPC) decoders are able to perform well in term of these metrics. In this thesis, the Modified Differential Decoding Binary Message Passing (MDD-BMP) algorithm of LDPC codes has been chosen to implement in mixed-signal domain. The goal of this research is to achieve energy-efficiency in LDPC decoding while maintaining high-throughput in an implemented design of reasonable effective area. The re-design of some digital parts of the LDPC decoder in analog domain is expected to offer energy-efficiency and high throughput. However, these benefits come at a cost of analog impairments, such as, different random mismatch between similar inverters arising from process variation during fabrication. The comparative contribution of these impairments on the BER performance of the decoder has been investigated. During the design of the decoder, an on-chip calibration scheme has been arranged and global routing of the tuning signals has been maintained to address these random mismatches. Furthermore, modulation of the decoding speed by off-chip tuning has been made possible. For the purpose of high-speed testing of the decoding process, enough on-chip memory has been placed to store 10 codewords and feed them to the decoder through a binary-weighted capacitor-based digital to analog converter. Design and placement of analog MUXes enable us to debug sensitive analog nodes inside the decoder from off-chip. Finally, the full process of the physical design of the decoder in TSMC 65nm has been almost fully automated in Cadence SKILL code. Over 100 simulations including parasitic capacitance of long wires in physical design yield an average decoding speed of approximately 2.04 ns in moderate speed mode, therefore, providing a high throughput of 134 Gb/s. Taking into account the average current drawn by the circuits during both the pre-charge phase and the decoding phase, the calculated average energy per bit consumed by the decoder is 1.267 pJ/bit