Design and FPGA Implementation of OFDM System with Channel Estimation and Synchronization

In wireless and mobile communications, multipath fading severely degrades the quality of information exchange. The orthogonal frequency division multiplexing (OFDM) technology is able to provide a high transmission data rate with enhanced communication performance at a relatively small bandwidth cost, together with proper estimation and compensation of channel effects. Therefore, it has been widely applied in many wireless and mobile networks, especially for the state-of-the-art communication standards. The unique structure of OFDM signals and the application of discrete Fourier transform (DFT) algorithm have significantly simplified the digital implementation of OFDM system. Among different kinds of implementations, field programmable gate array (FPGA) is a very cost-effective and highly flexible solution, which provides superior system performance and enables easy system upgrade. In this thesis, a baseband OFDM system with channel estimation and timing synchronization is designed and implemented using the FPGA technology. The system is prototyped based on the IEEE 802.11a standard and the signals is transmitted and received using a bandwidth of 20 MHz. With the help of the quadrature phase shift keying (QPSK) modulation, the system can achieve a throughput of 24 Mbps. Moreover, the least squares (LS) algorithm is implemented and the estimation of a frequency-selective fading channel is demonstrated. For the coarse estimation of timing, a modified maximum-normalized correlation (MNC) scheme is investigated and implemented. Starting from theoretical study, this thesis in detail describes the system design and verification on the basis of both MATLAB simulation and hardware implementation. Bit error rate (BER) verses bit energy to noise spectral density (Eb/N0) is presented in the case of different channels. In the meanwhile, comparison is made between the simulation and implementation results, which verifies system performance from the system level to the register transfer level (RTL). First of all, the entire system is modeled in MATLAB and a floating-point model is established. Then, the fixed-point model is created with the help of Xilinx’s System Generator for DSP (XSG) and Simulink. Subsequently, the system is synthesized and implemented within Xilinx’s Integrated Software Environment (ISE) tools and targeted to Xilinx Virtex-5 board. What is more, a hardware co-simulation is devised to reduce the processing time while calculating the BER for the fixed-point model. The present thesis is an initial work on the implementation part of an collaborative research and development (CRD) project of the Natural Sciences and Engineering Research Council of Canada (NSERC) sponsored by the WiTel Technologies, Ontario. It is the first and foremost step for further investigation of designing innovative channel estimation techniques towards applications in the fourth generation (4G) mobile communication systems