On the design and synthesis of differential clock distribution network

This research work focuses mainly on the design and synthesis of Differential Clock Distribution Networks (DCDNs). The Clock Distribution Network (CDN) plays an important role in synchronous systems. The network is spread all over the chip to synchronize its sub-systems. The system performance is influenced by the performance of its clock network. As technology advances and the complexity increases, a drastic growth in the chip complexity in the near future is expected. Thus designing a reliable CDN is becoming a must, and therefore all the design efforts should be utilized to efficiently design clock distribution networks. Of importance in chip design are low power and low noise concepts. Differential signaling scheme offers high noise immunity and since it is associated with signal amplitudes lower than the usual, it may contribute to reduce power consumption as well. Due to these potentials, the design and analysis of DCDN has been the focus of this research work. First, a line equivalent delay model based on the decoupling method is proposed to be able to route DCDNs with minimum skew. This part refers to the routing and synthesis of DCDNS. Later, new configurations for differential buffers based on body-biased transistors are proposed, which show better performance for future low voltage applications. Finally, a circuit and system design method that reduces the power consumption of DCDNs is proposed. This is accomplished in two steps: First circuit configurations that reduce the differential voltage swing giving less power consumption are introduced. Later, by reducing the supply voltage, a DCDN is designed which has the same power consumption as single-node CDNs, but has less skew variation in the presence of external noises such as power supply fluctuations