Binary operation procedure for thinning process and its VLSI implementation in a pixel array circuit

In this thesis, the design of a pixel array circuit for thinning process is presented. The research efforts of this work are on the two aspects: the processing algorithm and the circuit design. In the aspect of algorithm, a new thinning process is designed aiming at an easy implementation in a VLSI pixel array circuit. The computation is made in parallel and with a small number of direct data transfers among the neighboring pixels, which leads to a fast processing and fewer metal connections in the circuit. The effectiveness of the algorithm has been proved in the simulation. The other aspect of this work is the design of a pixel array circuit implementing the image acquisition and the proposed thinning proces