Edge detection in a pixel array circuit

Edge detection is commonly used to extract important features of an image, while providing a compression of image data, and thus it is one of the most important operations in image processing systems. Such a detection is usually implemented in a system of data processor(s) with its input image signals provided by a camera. However, in many applications, in which the constraints of speed, power and size of the hard-ware are critical, it will be favorable to implement the edge detection in a smart sensor, i.e. a pixel array circuit, in which each pixel operates in parallel with other to perform signal acquisition and processing. In this thesis, the design of a CMOS pixel array for edge detection is presented. The work of this thesis is in the two aspects, detection algorithms and circuit implementations. A new version of the algorithm for edge detection has been proposed, aiming at facilitating its implementation in an integrated circuit with simple inter-pixel connections and processing units in the pixels. It has been demonstrated that the proposed algorithm can result in a quality of the detection as good as the most commonly used detection algorithms. To implement this algorithm, a pixel array circuit has been designed with simple current-mode modules and logic gates in each pixel. The research effect in the circuit aspect is on solving the problems of the transistor mismatch, which makes identically-designed units behave non-uniformly, and charge injection in the current-mode circuits. With special compensation schemes implemented in the pixel circuit, the uniformity of the processing units integrated in the pixel array increased more than ten times, which improves significantly the quality of the operations in the process of the detection in the circuits. The pixel array circuit can be easily implemented with a standard CMOS technolog