A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications

Clocking is an important aspect of digital VLSI system design. The design of high-performance and low-power clocked storage elements is essential and critical to achieving maximum levels of performance and reliability in modern VLSI systems such as Systems on Chips (SoCs). In this thesis, a pulse-clocked double edge-triggered D-flip-flop (PDET) is proposed. PDET uses a new split-output true single-phase clocked (TSPC) latch and when clocked by a short pulse train acts like a double edge-triggered flip-flop. The P-type version of the new TSPC split-output latch is compared with existing TSPC split-output latches in terms of robustness, area, and power efficiency at high-speeds. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches. The novel double edge-triggered flip-flop uses only eight transistors with only one N-type transistor being clocked. Compared to other double edge-triggered flip-flops, PDET offers advantages in terms of speed, power, and area. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Period-Power product is reduced by 56%-63% compared to other double edge-triggered flip-flops. Simulations are performed using HSPICE in CMOS 0.5 om technology. This design is suitable for high-speed, low-power CMOS VLSI design applications