An FPGA implementation of RM-BTC Codec using Log-MAP algorithm

Due to their powerful error correcting capability and superior coding gain, Turbo Codes are used in 3rd generation wireless and satellite communication systems. For these applications, efficient implementation of Turbo Codes, i.e., development of codec providing high throughput with small chip area and low power consumption is of growing importance. In this thesis, Turbo Code using Reed-Muller code as its constitute code is implemented in VHDL and logic synthesis is executed. The Max-Log-MAP algorithm is used due to its significantly reduced complexity and negligible performance degradation from MAP algorithm. The implementation of codec mainly focuses on achieving the smaller chip area and lower power dissipation, and target to device Virtex-E FPGA. For this purpose, the system and module level optimization of codec architecture is carefully considered through the parallelism and pipeline, interleaving technique, function unit sharing and memory access. The quantization and finite accuracy are also discussed. The simulation in RTL level on a wide variety of test vectors is done, and results show that the encoder/decoder execute properly and correct functionality is realized. The synthesis reports show that chip utilization is reasonable and more resource remains for future improvement