Handling large data storage in synthesis of multiple FPGA systems

Implementing DSP algorithms on single or multiple FPGAs has the advantages of short time to market, non-recurring engineering, and fast prototyping. Most of today's FPGAs provide fast arithmetic operations and large enough internal RAM storage that makes them very appealing to prototyping large systems, even building DSP applications. So having a good architecture to begin with is a good asset to engineers. This thesis investigates the issues of handling large data storage in the synthesis of multiple FPGA systems especially in digital signal/image processing applications. In these applications very simple to complex algorithms are performed on large amounts of data - image. An efficient way to store and access these data, the storage of intermediate variables locally or on RAM, is presented. The maximum pipeline level is extracted based on this storage and access scheme. A generic architecture for execution of arbitrary DSP algorithms with multiple memory banks is proposed. An ILP formulation for assigning memory banks to variables is presented. For demonstration purposes, a pipelined complex FFT has been developed in VHDL and the efficient storage and access order for this algorithm is presented. Also, based on these storage/access orders, the generation of addresses is done using hardware address generators