A Multicore Neuromorphic Chip Design Using Multilevel Synapses in 65nm Standard CMOS Technology

University of Minnesota M.S. thesis. June 2015. Major: Electrical Engineering. Advisor: Chris Kim. 1 computer file (PDF); v, 38 pages.Neuromorphic research community is focused on designing a hardware which is as efficient as biological brain in terms of performance, power and area. It opens up opportunities to optimize these designs at all levels from architecture to devices. We propose a novel architecture to have tight integration between neurons and synapses. Our 32K bit neuromorphic chip with 256 axons and 256 neurons demonstrates 4 neuromorphic cores operating in a completely parallel fashion. Eflash memory core representing synapses saves power and area. The Non-volatility of eflash consumes zero static power. The ability to store multi-levels of weights in a single cell makes the array denser. Unlike flash technology, eflash doesn’t require specialized fabrication process, hence the neuromorphic chip is implemented in 65nm standard CMOS technology. The current sensing neurons with parallel reading scheme makes the neuronal operation several orders of magnitude faster than state-of-the-art neuromorphic designs