Digital signal processing platform based on a novel dynamically reconfigurable array

Dynamically reconfigurable processors are attracting significant interest in the semiconductor industry as they are promising to provide a new level of trade-off between the conflicting parameters of performance, flexibility, silicon area, power consumption and Non-Recurring Engineering (NRE) costs. The work presented in this thesis addresses two major areas in the design of a platform based around a novel reconfigurable array. Reconfigurable architectures generally suffer from poor code densities with very wide instruction words. The first project is focused on how best to reduce the program memory footprint, in order to reduce area and potentially the power consumption, thus making the product marketable in the mobile phone industry. Existing compression techniques are found to be unsuitable for the target architecture, thus new schemes are devised. The second project is concerned with porting DSP applications to the reconfigurable architecture to gain the best trade-off between performance (i.e. throughput) and cost (in terms of the number of functional units/on-chip resources used). This ensures the final product delivers the required performance without sacrificing flexibility or cost points, thus yielding a competitive product. Third party proprietary DSP algorithms as well as open source algorithms are ported in C. Issues have been identified and suggestions are put forward for tackling the issues on the architecture and associated tools