A Study of Hardware Acceleration in System on Chip Designs using Transport Triggered Architecture

Transport Triggered Architecture is a processor design philosophy where the datapath is visible for the programmer and the program controls the data transfers on the path directly. TTA processors offer a good alternative for application specific task as they can be easily optimized for a given application. TTA processors, however, adjust poorly to dynamic situations, but this can be compensated with external hosting. Fast Fourier transform is an approximation of the Fourier transform for converting time domain data into frequency domain. Fast Fourier transform is needed in many digital signal processing applications. One example of the usage of the transform is the LTE network access schemes where the symbols transmitted over the air interface are constructed with the fast Fourier transform and again demodulated as they are received. The study makes use of Nokia Co-Processor as the host for TTA processor and proposes alternatives for different architectures for the usage of the TTA processor inside a practical design where data is being moved over interconnections and memories. One proposed architecture is selected for implementation and the construction of this architecture is discussed regarding implementing the needed hardware and software to run the Fourier application on TTA with data being fetched and written back in system memory. Lastly, the performance of the implementation is discussed