Passivation of Textured Silicon Wafers:Influence of Pyramid Size Distribution, a-Si:H Deposition Temperature, and Post-treatment

AbstractIn this study we focus on optimizing the passivation of pyramid textured n-type crystalline silicon (c-Si) wafers by deposition of intrinsic amorphous Si (a-Si:H(i)) layers. By statistical analysis of the pyramid size distribution it is revealed that a decreased fraction of small pyramids leads to longer minority charge carrier lifetimes and, thus, a higher Voc potential for solar cells. Further, we demonstrate that optimized parameters for the deposition of a-Si:H(i) layers on planar Si(111) wafers can be transferred to the a-Si:H deposition on random pyramid textured Si(100) wafers exhibiting facets with {111} orientation. In particular the influence of the deposition temperature on the optical layer properties is elucidated. Furthermore, the favorable impact of post-deposition plasma-hydrogenation and annealing on the charge carrier lifetime (> 5ms) and the implied open-circuit voltage (up to 738mV) are demonstrated