An asynchronous resilient circuit template and automated design flow

2019-02-14As advancements in process technology slow and the ubiquity of mobile and embedded devices increases, chip designers are looking to new technologies to stretch the energy efficiency of the standard silicon-based semiconductor. The increased focus on energy efficiency and decreased ability to provide efficiency through process shrinks has led the industry to look towards near-threshold and sub-threshold design paradigms to fuel the next generation of low-power devices. However, adding margins to address increased delay variation in these regions of operation often overshadow efficiency gains. Resilient circuit templates have been proposed as one general solution to reducing the required margins of synchronous designs, where timing violations are allowed and errors introduced in the datapath by these violations are corrected at a later time to ensure data integrity. ❧ However, none of these synchronous resilient solutions have gained industry traction. Many have suffered from metastability or require modifying the architecture to add replay-based logic that recovers from timing errors, which leads to high timing error penalties and poses a design challenge in modern processors. Therefore, an asynchronous resilient circuit template, Blade, is proposed that addresses the concerns and problems of existing resilient solutions; it is robust to metastability issues, requires no replay-based logic, and has low timing error penalties. The Blade template’s timing assumptions and requirements are analyzed and a generic approach for modeling the performance benefits of applying Blade to an existing circuit is provided. ❧ In addition, complex design flows are a common barrier to using asynchronous circuits in industry. Therefore, an automated design flow is proposed that synthesizes synchronous RTL designs to gate-level asynchronous Blade designs using existing, commercially available synchronous tools. The various steps of the design flow are described in detail and its application to a 3-stage MIPS CPU and light-weight encryption cores is explored. In addition, simple optimizations to reduce the area overhead associated with converting an existing design to Blade are examined