Improving reliability, power and performance in hardware transactional memory

2018-11-15Transactional Memory (TM) enhances the programmability as well as the performance of parallel programs running on a multi-core or multi-processor system. To achieve this goal, TM adopts a lock-free approach, in which mutually exclusive events are executed optimistically and corrected later if violations of mutual exclusion are detected. As a result TM disposes of the complexities of conventional locking mechanisms, especially when multiple locks must be held simultaneously. Some proposals such as Transactional Memory Coherence and Consistency (TCC) and Bulk extend the applicability to cache coherence and consistency with cache coherence protocols relying on the optimistic approach of TM. ❧ To realize TM’s full potential, we propose various architecture schemes in this dissertation, targeting improvements for reliability, power and performance of HTM systems. First, we introduce transaction-based reliability protecting processor cores from transient errors. Second, we propose a Dynamic Transaction Issue (DTI) scheme that can be easily implemented on top of existing HTM systems, saving the power dissipation and energy consumption associated with transaction aborts. Third, we refine our DTI scheme with a new approach based on Fine Grain Prediction and Scheduling (FGPS), improving the prediction accuracy of the prior proactive scheduling algorithms. Lastly, we target transaction commit, which is the common case in most benchmark applications, to improve the execution time of successful transactions