AbstractWe present deterministic upper and lower bounds on the slowdown required to simulate an (n, m)-PRAM on a variety of networks. The upper bounds are based on a novel scheme that exploits the splitting and combining of messages. This scheme can be implemented on an n-node d-dimensional mesh (for constant d) and on an n-leaf pruned butterfly and attains the smallest worst-case slowdown to date for such interconnections, namely, O(n1/d(log(m/n))1-1/d) for the d-dimensional mesh (with constant d) and O(nlog(m/n)) for the pruned butterfly. In fact, the simulation on the pruned butterfly is the first PRAM simulation scheme on an area-universal network. Finally, we prove restricted and unrestricted lower bounds on the slowdown of any determi...
A simulation scheme for (n, m)-PRAM computation is devised, based on an interconnection network orga...
Parallel Random Access Machine, PRAM, is the most popular abstract model of the parallel computation...
Andrews introduced a number of techniques for automaticallyhiding latency when performing simulation...
We present deterministic upper and lower bounds on the slowdown required to simulate an (n,m)-PRAM o...
We present deterministic upper and lower bounds on the slowdown required to simulate an (n;m)- PRAM ...
This paper describes an improved scheme for PRAM simulation on the mesh. The simulation algorithm ac...
AbstractWe show a lower bound of Ω(min{log m, √n}) on the slowdown of any deterministic emulation of...
We present a constructive deterministic simulation of a PRAM with n processors and m = n^alpha; shar...
The Parallel Random Access Machine (PRAM) is an abstract parallel machine consisting of a synchrono...
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with ...
A deterministic scheme for the simulation of (n, m)-PRAM computation is devised. Each PRAM step is s...
We present efficient emulations of the CRCW PRAM on a large class of processor interconnection netwo...
The problem of simulating a PRAM with $n$ processors and memory size $m \geq n$ on an $n$-node boun...
The PRAM is a shared memory model of parallel computation which abstracts away from inessential engi...
This paper studies relations between the parallel random access machine (pram) model, and the reconf...
A simulation scheme for (n, m)-PRAM computation is devised, based on an interconnection network orga...
Parallel Random Access Machine, PRAM, is the most popular abstract model of the parallel computation...
Andrews introduced a number of techniques for automaticallyhiding latency when performing simulation...
We present deterministic upper and lower bounds on the slowdown required to simulate an (n,m)-PRAM o...
We present deterministic upper and lower bounds on the slowdown required to simulate an (n;m)- PRAM ...
This paper describes an improved scheme for PRAM simulation on the mesh. The simulation algorithm ac...
AbstractWe show a lower bound of Ω(min{log m, √n}) on the slowdown of any deterministic emulation of...
We present a constructive deterministic simulation of a PRAM with n processors and m = n^alpha; shar...
The Parallel Random Access Machine (PRAM) is an abstract parallel machine consisting of a synchrono...
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with ...
A deterministic scheme for the simulation of (n, m)-PRAM computation is devised. Each PRAM step is s...
We present efficient emulations of the CRCW PRAM on a large class of processor interconnection netwo...
The problem of simulating a PRAM with $n$ processors and memory size $m \geq n$ on an $n$-node boun...
The PRAM is a shared memory model of parallel computation which abstracts away from inessential engi...
This paper studies relations between the parallel random access machine (pram) model, and the reconf...
A simulation scheme for (n, m)-PRAM computation is devised, based on an interconnection network orga...
Parallel Random Access Machine, PRAM, is the most popular abstract model of the parallel computation...
Andrews introduced a number of techniques for automaticallyhiding latency when performing simulation...