Design and FPGA Synthesis of Three Stage Telecommunication Switching in HDL Environment

AbstractTelecommunication networks are based on crossbar switching structure. Non-blocking crossbar switching structure is used crosspoint switch fabric ICs. High performance non-blocking matrixes cross point switches are use to avoid the congested path to the output, and eliminate the bandwidth problem of one at a time. Telecommunication switching uses multistage crossbar switching to overcome the limitations of individual chips or boards. The research paper focuses on the FPGA implementation of 64×64 three stage telecommunication switching. The generic architecture scheme is followed to implement 64×64 three stage network configuration, with 64 inlets and 64 outlets as cluster size. The design is developed with the help of Xilinx ISE 14.2, software, synthesized on Virtex- 5 FPGA, and function simulation is carried out in Modelsim 10.1b student edition. Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to develop the design