AbstractIn this paper, we present a number of algorithms to test the instruction decoding function of microprocessors. The algorithms are based on the knowledge of some timing and control information available to users through microprocessor manuals and data sheets. The tests are functional in nature. We also establish the order of complexity of the algorithms presented in this paper. As an example, the test complexity for a microprocessor is computed and the results are compared with a known algorithm
We propose a new on-line testing approach for the control logic of high performance microprocessors....
All microprocessor units have a similar architecture from which a basic test philosophy can be adopt...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
AbstractIn this paper, we present a number of algorithms to test the instruction decoding function o...
With the growing use of the microprocessors the problematics of testing become more and more import...
A methodology for on-line testing of microprocessors without using massive redundancy is developed. ...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
The gate-level testing also called low-level testing is generally appropriate at the design time and...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
Abstract—The main problem is test data generation for arithmetic subsystem testing of CPUs MIPS64. A...
This paper describes results obtained by simulation, in order to evaluate the efficiency of very sim...
Design modifications in microprocessors are recommended to simplify the task of testing them in the ...
The problems met when testing microprocessors (unknown equivalent logical schematics and fault hypot...
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach...
The paper is dealing with the in-field test of the decode unit of RISC processors through functional...
We propose a new on-line testing approach for the control logic of high performance microprocessors....
All microprocessor units have a similar architecture from which a basic test philosophy can be adopt...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
AbstractIn this paper, we present a number of algorithms to test the instruction decoding function o...
With the growing use of the microprocessors the problematics of testing become more and more import...
A methodology for on-line testing of microprocessors without using massive redundancy is developed. ...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
The gate-level testing also called low-level testing is generally appropriate at the design time and...
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, ...
Abstract—The main problem is test data generation for arithmetic subsystem testing of CPUs MIPS64. A...
This paper describes results obtained by simulation, in order to evaluate the efficiency of very sim...
Design modifications in microprocessors are recommended to simplify the task of testing them in the ...
The problems met when testing microprocessors (unknown equivalent logical schematics and fault hypot...
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach...
The paper is dealing with the in-field test of the decode unit of RISC processors through functional...
We propose a new on-line testing approach for the control logic of high performance microprocessors....
All microprocessor units have a similar architecture from which a basic test philosophy can be adopt...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...