Design Of Hardware Efficient High Speed Multiplier Using Modified Ternary Logic

AbstractThis paper presents a novel design for a parallel multiplier using ternary logic based on reduced routing and chip area, an alternative to conventional binary logic. The methodology of ternary logic is used for the design of standard inverter(STI), negative inverter (NTI), positive inverter(PTI), NAND and NOR gates. The basic gates are then used for design of multiplier with partial product reduction elements in the same logic. As a further optimization, we have implemented the multiplier with a combination of binary and ternary logic to enjoy the benefits of two. The proposed and optimized designs are designed using VHDL and synthesized using SYNOPSIS software. Extensive simulation results show that the proposed modified ternary logic designs consume significantly lower power and delay compared to ternary designs