Thermal-Electrical finite element analysis of nanometric copper vias under high fluence stress

This paper presents the development of a thermal-electrical finite element (FE) model with the objective to analyze failure mechanisms responsible of physical degradation (void, copper silicate formation, etc.) caused by high fluence stress of 90nm copper vias for FinfET devices. Indeed in [1], this physical degradation was interpreted as a main consequence of Joule effect, however their employed model reached too low temperatures to explain the observed physical degradation. In order to confirm this, the steady-state FE model developed in this work computes the temperature increase and distribution caused by high electrical current density flowing through a copper contact, considering non-ideal thermal and electrical interfaces. In addition, a sensitivity analysis is performed as a way to identify critical failure parameters. The temperature response of the model to independent variation of electrical resistivity of studied materials, and interfacial electrical and thermal conductance between the copper contact and its diffusion barrier were obtained. The decrease of interfacial electrical conductance triggers steady-state temperatures over copper and silicate melting points and, in consequence leads to temperature high enough to explain the physical degradation.