Modeling and simulation of Cu diffusion and drift in porous CMOS backend dielectrics

With the advent of porous dielectrics, Cu drift-diffusion reliability issues in CMOS backend have only been exacerbated. In this regard, a modeling and simulation study of Cu atom/ion drift-diffusion in porous dielectrics is presented to assess the backend reliability and to explore conditions for a reliable Resistive Random Access Memory (RRAM) operation. The numerical computation, using elementary jump frequencies for a random walk in 2D and 3D, is based on an extended adjacency tensor concept. It is shown that Cu diffusion and drift transport are affected as much by the level of porosity as by the pore morphology. Allowance is made for different rates of Cu dissolution into the dielectric and for Cu absorption and transport at and on the inner walls of the pores. Most of the complex phenomena of the drift-diffusion transport in porous media can be understood in terms of local lateral and vertical gradients and the degree of their perturbation caused by the presence of pores in the transport domain. The impact of pore morphology, related to the concept of tortuosity, is discussed in terms of “channeling” and “trapping” effects. The simulations are calibrated to experimental results of porous SiCOH layers of 25 nm thickness, sandwiched between Cu and Pt(W) electrodes with experimental porosity levels of 0%, 8%, 12%, and 25%. We find that porous SICOH is more immune to Cu+ drift at 300 K than non-porous SICOH