This paper presents the design of hardened translation lookaside buffer based on Spaced Transistor Groups (STG) DICE cells in 65-nm bulk CMOS technology. The resistance to impacts of single nuclear particles is achieved by spacing transistors in two groups together with transistors of the output combinational logic. The elements contain two spaced identical groups of transistors. Charge collection from particle tracks by only transistors of just one of the two groups doesn’t lead to the cell upset. The proposed logical element of matching based on the STG DICE cell for a content-addressable memory was simulated using TCAD tool. The results show the resistance to impacts of single nuclear particles with linear energy transfer (LET) values up...
Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-node ups...
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single ev...
As technology scales deep in submicron regime, CMOS SRAM memories have become increasingly sensitive...
This paper presents the design of a static RAM cell in 65 nm CMOS technology. A good level of radiat...
Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A ...
Comparison elements on base the STG DICE cell and the logical element “Exclusive OR” for a content-a...
Abstract In this paper, we present a new radiation tolerant CMOS standard cell library, and demonst...
Static random access memory cells (SRAM) are high-speed semiconductor memory that uses flip-flop to...
In radioactive environments, particle strikes can induce transient errors in integrated circuits (IC...
This paper proposes a new design method to enhance the radiation hardness of circuits for the next g...
Technology scaling of CMOS devices has made the integrated circuits vulnerable to single event radia...
In the electronics space industry, memory cells are one of the main concerns, especially in term of ...
A 512 kbit static random access memory has been designed and fabricated in a single-poly, six-metal ...
From the first integrated circuit which has 16-transistor chip built by Heiman and Steven Hofstein i...
Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to ...
Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-node ups...
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single ev...
As technology scales deep in submicron regime, CMOS SRAM memories have become increasingly sensitive...
This paper presents the design of a static RAM cell in 65 nm CMOS technology. A good level of radiat...
Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A ...
Comparison elements on base the STG DICE cell and the logical element “Exclusive OR” for a content-a...
Abstract In this paper, we present a new radiation tolerant CMOS standard cell library, and demonst...
Static random access memory cells (SRAM) are high-speed semiconductor memory that uses flip-flop to...
In radioactive environments, particle strikes can induce transient errors in integrated circuits (IC...
This paper proposes a new design method to enhance the radiation hardness of circuits for the next g...
Technology scaling of CMOS devices has made the integrated circuits vulnerable to single event radia...
In the electronics space industry, memory cells are one of the main concerns, especially in term of ...
A 512 kbit static random access memory has been designed and fabricated in a single-poly, six-metal ...
From the first integrated circuit which has 16-transistor chip built by Heiman and Steven Hofstein i...
Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to ...
Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-node ups...
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single ev...
As technology scales deep in submicron regime, CMOS SRAM memories have become increasingly sensitive...