Structural Redundancy and Design Space Exploration Method for the Hardware Components with Fault Mitigation Design

Fault mitigation for modern embedded systems is a necessary feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault protection that need to be implemented. Another parameter of embedded system – area. It is one of most critical parameters for SoC in embedded systems and is strongly constrained. Increasing fault protection leads to growing of the SoC’s area. In this situation, it is necessary to know how strong the fault mitigation is and how it effects on the area. We propose the method for development of hardware components that can help to evaluate project from point of area constraints and fault probability requirements