FULL ADDER/ SUBTRACTOR USING REVERSIBLE LOGIC

Reversible logic is now-a-days emerging as an im-portantresearch area over conventional logic. It is having varietyof applications in fields of Digital Signal Processing, QuantumComputing and Low Power CMOS Design. Irreversiblelogic circuits dissipate heat for every bit of information thatis lost. It is not possible to think of quantum computingwithout implementation of reversible logic. The main purposesof designing reversible logic are to decrease quantumcost, depth of the circuits and the number of garbage outputs.This paper provides the Full adder/subtractor thatuses Half adder/ subtractor with minimum constant inputsand minimum garbage outputs. Thus the proposed architectureFull Adder/ Subtractor is having minimum numberof Constant Inputs and Garbage Outputs than the Existingarchitecture.