A holistic approach of focus control for 193nm immersion lithography for critical layers in 28nm and 14nm FD-SOI technologies

La complexification des intégrations sur les puces électroniques et la course à la miniaturisation sont les deux moteurs actuels de la microélectronique. Les limites optiques de la lithographie sont déjà atteintes depuis longtemps. Ainsi, la fabrication doit aussi être contrôlée de plus en plus étroitement afin d’éviter des variabilités qui nuiraient au bon fonctionnement du produit. Cette thèse présente une approche holistique du contrôle d’un des paramètres les plus importants de la photolithographie : le focus. Celui-ci est directement lié à la qualité de l’image transférée dans la résine photosensible pendant l’exposition. Son contrôle est donc primordial. Les sources de variabilités du focus sur le wafer sont multiples et diverses mais le cas particulier de la topographie du substrat a été privilégié dans cette étude. L’approche holistique de cet effet en particulier a conduit à l’utilisation d’outils de « data mining » telle la régression par la méthode des moindres carrés partiels qui a permis de pointer les principales causes de cette topographie, de créer un modèle prédictif de la topologie mais aussi d’évaluer des solutions d’améliorations comme l’amélioration des corrections qu’effectue le scanner permettant un meilleur contrôle généralisé de toutes les technologies sans toutefois changer l’intégration et le design ou encore la mise en place d’une méthode qui permet d’évaluer les erreurs de focus sur le wafer sans pour autant avoir recours à des mesures intensives sur silicium. D’autres solutions permettent de corriger les facteurs de risques à la source en modifiant le design afin de limiter la formation de la topologie de surfaceThe increasing complexity in chip integration (co-integration, increasing diversity of matérials…) and the race to dimension shrinkage are the two main drivers of research in microelectronics today. The optical limitations of lithography have been reached some years ago so that double patterning is now a typical process flow in production and helps reducing pattern size and increasing design density. Because of these, the manufacturing itself needs to be more tightly controlled in order to avoid marginalities. Which will affect the chip operation. The cross-effects between these elements are more numerous and their ratio in the total budget is larger whereas the needs for tighter process control are rising. This thesis presents a holistic approach of the control of one of the main parameters for photolithography: focus. It is directly linked to the quality of the image transferred into the photoresist during exposure. Its control is then essential. Variability sources for focus are manifold and diverse: laser, mask, optical column, servo-controllers, wafer flatness, integration, design, substrate reflectivity, material quality etc. All these are added to each other, leading to the creation of defects which can be catastrophic such as shorts. The first objective of this work was to show current challenges raised by STMicroelectronics new technologies, specifically photolithography-wise and focus-wise. A budget breakdown of two critical processes (Metal line patterning in 28nm FD-SOI and Contact patterning for 14nm FD-SOI) has been established which gives the impact of every effect. The product layout effects were evaluated to represent up to 20% of the complete budget and 50% of its intra-chip component. Topography contributes to a large part of these effects and offline measurements showed up to 32nm 3s of height variation in a single field. This may lead to local defocuses of the same order of magnitude. The usable depth of field being about 60 to 70nm for the studied layers, it is clear that focus control is really tight here. The holistic approach of topology leaded to the use of data mining tooling as PLS regression (Partial least Square). It allowed the highlighting of main causes of topography, the creation of a predictive model of topology and the evaluation of several improvement solutions. One may distinguish “palliative” and “curative” solutions. In the first category, on may put scanner levelling improvements which might be effective for every technology without any modification to make on integration and design. The emulated wafer map methodology providing on-product focus non-uniformities without any measurements is also a solution for investigation. “Curative” solutions may concern the mitigation of risk factors by modifying the design topography built-up main factor