Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies

在先進製程中，維持時間錯誤因為製程變異、電源雜訊和溫度影響日益嚴重而逐漸備受重視。在鰭式場效電晶體中，有些缺陷會造成延遲時間減少，進而造成維持時間錯誤。雖然在電路中的短路徑上插入緩衝器可以減少維持時間錯誤的發生，但這些額外的緩衝器會增加額外的面積與電源消耗。在此論文中，我們提出基於路徑的維持時間錯誤模型。此錯誤模型中的錯誤數量是與電路中的暫存器數量呈線性正比。我們也呈現傳統的測試向量產生器並不足夠並提出相對應的電路模型，使之能夠給自動測試向量產生器產生穩定性測試向量。為了產出針對維持時間錯誤模型之穩定性測試向量，我們提出穩定性測試向量產生器、錯誤模擬器。實驗結果顯示，我們的測試向量與商業用一次偵測測試向量比較，我們的測試圖騰在穩定性錯誤涵蓋率上好38%，測試向量長度少42%。。Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and temperature. Defects in FinFET technology may also casue hold-time faults. Although delay padding can eliminate above issues, the extra area and power is needed without any contribution to performance. In this thesis, a path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. And the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional path delay fault ATPG is not sufficient for hold-time faults. A hold-time fault ATPG is presented to generate robust test patterns. Experiments on large benchmark show that our test patterns are 42% shorter while 38% better in robust fault coverage than 1-detect stuck-at fault test sets. The results justify the need for hold-time fault ATPG