Design of Highly Energy-Efficient Continuous-Time Delta-Sigma Modulators

本論文以設計高效能連續時間三角積分調變器為目標，針對調變器的迴路濾波器架構、量化器架構以及回授路徑線性度的校正電路，提出了改善的方法。論文第一部份提出了使用單級運算放大器濾波器以及時域量化器的架構，實現了一個低功耗連續時間三角積分調變器，所提出的迴路濾波器架構使用了一個運算放大器以及改進過的雙T型被動回授網路，達到二階共振功能以及前饋路徑。搭配提出的雙T型被動回授網路，並且透過適當的選取回授路徑的注入點，可以在不增加額外的硬體下，就可以達成延遲迴路補償。 此外，為了降低量化器的功率消耗並且同時解決回授數位類比轉換器的線性度問題，本論文提出了一個內建動態元件匹配功能的時域量化器，取代原先一般調變器常用的快閃式量化器以及用於校正回授路徑線性度的動態元件匹配電路，所提出的時域量化器可以同時達到量化迴路濾波器的輸出以及線性化回授數位類比轉換器的目的。 論文第二部份則是基於第一個設計，更近一步將雙步階的概念應用於時域量化器，降低時域量化器的功耗以及硬體面積，為了更進一步增加信號頻寬，論文第三部份的設計是使用兩個運算放大各自搭配不同架構的雙T型網路，達到四階雜訊整形的功能，量化器方面則是採用內建隨機亂數加權平均電路之時域內插快閃式量化器來達到低功耗的訴求，並同時解決量化器以及回授路徑的線性度問題。 此論文中共實現了三個三角積分調變器，皆使用台積電90奈米互補式金氧半製程所實現，三個調變器分別操作於300MHz, 256MHz以及320MHz的取樣頻率，在8.5MHz, 8MHz和13MHz的信號頻寬下，最大可以達到67.2 dB, 69.6 dB, 68.1 dB 的訊號雜訊比。To achieve highly energy-efficient designs of continuous-time delta-sigma modulators (CTDSMs), the thesis proposes several new techniques and applies those to the loop filter, quantizer and linearization circuits used in the feedback DAC. In the first part of the thesis, a power-efficient CTDSM employing a single-amplifier biquad (SAB)-based loop filter topology and a time-domain quantizer is proposed. With single amplifier and the modified twin-T passive feedback network, the proposed SAB-based loop filter can achieve 2nd-order resonating function and feedforward path concurrently. By choosing the feedback node properly, the excess loop delay compensation path can be realized without additional hardware. Meanwhile, to resolve the nonlinearity issue of feedback DAC and lower the power consumption of the quanitzer, a time-domain quantizer embedded with data-weighted-averaging (DWA) function is proposed to replace a flash-type quantizer and DWA shuffling logics. The proposed quantizer can digitize the analog output signal of the loop filter and linearize the feedback digital-to-analog converter concurrently. Based on the first design, the second part of the thesis proposed a CTDSM employing a 2-step time-domain quantizer to further reduce the power consumption and hardware cost. In the third part of the thesis, the CTDSM adopted two SAB-baed filters with two different T networks to achieve the 4th-order noise shaping. A flash-type quantizer with the interpolating technique is used to digitize output of the loop filter. Furthermore, a random-skipped incremental data weighted averaging (RS-IDWA) function is proposed to address the linearity issue of quantizer and feedback DAC. Fabricated in 90-nm CMOS and operated at 300MHz, 256MHz and 320MHz, the proposed CTDSMs can achieve peak SNDR of 67.2 dB, 69.6 dB, and 68.1 dB over a 8.5 MHz, 8 MHz and 13 MHz signal bandwidth, respectively