Comprehensive Optimization Algorithms for Directed Self-Assembly (DSA)-Aware Redundant Via Insertion

Directed self-assembly (DSA) lithography technology, which has shown its strong potential for contact/via fabrication, is the most promising candidate patterning dense layout for next generation lithography in sub-10 nm technology nodes. On the other hand, post-routing redundant via insertion process adding a redundant via adjacent to a single via has become an important semiconductor manufacturing procedure highly recommended by foundries to increase yield and circuit reliability. However, existing redundant via insertion algorithms are not suitable for DSA since they could seriously decrease via manufacturability. Although the first ILP-based algorithm for redundant via insertion considering DSA has been proposed in [14], this method suffer from high computational complexity and may not efficient enough for a large and complicated circuit design. In this work, we proposed two efficient algorithms to simultaneously optimize DSA guiding templates and redundant via insertion rate. A graph-based approach is first presented to find a near-optimal solution of DSA-aware redundant via insertion of a given layout in linear time. Then, an advanced integer linear programming (ILP)-based algorithm is proposed to find an optimal solution. Moreover, we utilized wire perturbation to further enhance the quality of DSA-aware redundant via insertion. Experimental results show that our algorithms can effectively optimize the redundant via insertion rate and improve DSA manufacturability. Compared to the first ILP-based method [14], our graph algorithm and ILP approach can achieve 40X and 2X speed-up respectively