A TSV-Based with Multi-Layer Transmission for Low Power Strategy 3D SRAM Design

隨著製成演進，由於線電容線電阻與漏電流影響增加，使得我們難以持續追隨著摩爾定律。根據國際半導體技術路程組織所提出的超越摩爾定律路程，新的技術像是多閘極電晶體、奈米碳管、三維積體電路等方法被提出來，而我們選擇三維積體電路技術來解決上述這樣的問題。一種提供垂直連接的製程技術稱為矽晶穿孔，其已經成為三維堆疊元件的一個有前景的解決方案。 本論文我們提出了利用多晶矽傳輸且支援多層傳輸並且去除預充電機制的傳輸方法。三維記憶體主要將兩個完整記憶體堆疊起來並用矽晶穿孔做連接。此電路採用是主層與僕層的連接架構，上層的訊號透過矽晶穿孔傳到下層，傳統上如果是直接傳輸，當電路之輸入/輸出矽晶穿孔數量很大時，對於每個矽晶穿孔充電浪費很多功耗；故基於此議題，本設計提供一三維晶片感測及電荷共享方法以解決該問題。可以降低在矽晶穿孔傳輸介面上產生的功耗，以及利用偵測控制時脈達成支援三維堆疊多層之情形。 我們使用台積電九十奈米混合訊號製成來完成了一個由六萬四千字元所組成的三維靜態隨機存取記憶體，量測結果顯示在堆疊四層時比起單端輸出有30%的功耗降低。It’s difficult to keep following the Moore’s Law due to the larger effect of the wire resistance, wire capacitance and leakage current. According to the ITRS More-than-Moore Roadmap, the new type of technology should be developed such like FinFET, Carbon tube of 3D-IC. We choose 3D-IC to solve the mentioned problem. The TSV technology for vertical transmission is introduced to the 3D-IC process, and become a popular solution to the 3D-IC stacking issue. In the thesis, we proposed a TSV-based multi-layer transmission with free-pre-charge operation scheme. 3D-SRAM is constructed with multi-layer whole memory array and TSV for stacking. This design follows the single master scheme to control the master layer and slave layer transmission. The traditional transmission such like single-ended would cost a lot of power due to rail-to-rail transmission, especially in the wild I/O situation. Although the differential transmission creates a small swing voltage to reduce the power consumption in TSV, the pre-charge cycle in every read operation would cost tremendous power, too. Our scheme provides a free-pre-charge architecture with charge recycle and tracking systems. The proposed 64kb 3D-SRAM was fabricated in TSMC 90nm mix-signal process with 2, 4, 8, 16 layers modeling ability. The proposed design 30% power reduction, compare to single-ended transfer scheme