Layout Data Compression Algorithm and Its Hardware Decoder Design for Multiple Electron-Beam Direct-Write Systems

The advances in optical projection lithography have ensured the steady continuation of Moore''s law. However, the wavelength of light sources has reached the lowest limit of 193-nm, and optical diffraction has become a major problem. Thus, other cost effective solutions are urgently needed. Electron-beam maskless lithography is a powerful technology capable of very-high resolution writing. However, electron-beam maskless lithography suffers from slow electron-beam scanning process and low throughput. In recent years, new research on multiple electron-beam direct-write systems that use massively parallel electron-beam emitters to achieve fast scanning process and high WPH has gained popularity. In multiple electron-beam direct-write systems, one of the technical challenges is to transfer very large amounts of electron-beam layout data that controls electron-beam emitters from the data centers to multiple electron-beam direct-write systems. Furthermore, due to the enormous data transfer rates, a large number of hardware decoders are required in multiple electron-beam direct-write systems. Each hardware decoder must be able to decompress EBL data at high data rates, and the hardware resource requirements should be low so that the cost of implementing and operating the multiple electron-beam direct-write systems can be minimized. In this dissertation, a lossless electron-beam layout data compression algorithm, LineDiff Entropy, and its low-complexity high-performance hardware decoder for multiple electron-beam direct-write lithography systems are proposed. The algorithm compares consecutive data scanlines and encodes the data based on the change/no-change of pixel values and the lengths of pixel sequences. Then, the compaction steps of data omission, merging, and encoding of consecutive long identical scanlines are applied. Then, custom prefix codes are assigned to data with high occurrence frequency. The hardware decoder is designed as three circuit blocks that perform entropy decoding, de-compaction, and electron-beam layout data generation through parallel outputs. The hardware decoder only requires minimum resource.The results demonstrate that our algorithm can achieve excellent compression performance and that the hardware decoder can decompress data at very high data rates