Research on GaAs pHEMT Low Noise Amplifiers for Ka-band Applications

本論文說明一個設計在Ka頻段的低雜訊放大器。所應用的系統為衛星通訊地面相位陣列前端系統，接收頻率為19.2 GHz，發射頻率則為29 GHz。為了要選擇接收左旋極化或右旋極化之訊號，此低雜訊放大器需提供訊號路徑的切換功能。 在系統規格的要求之下，所訂定的低雜訊放大器規格如下：中心頻率為19.2 GHz，頻寬為3 GHz，增益大於18 dB，雜訊指數小於1.3 dB，直流功耗小於21 mW。為了避免功率放大器的輸出訊號溢漏至接收器端，造成低雜訊放大器的非線性效應，於電路中對應到29 GHz處設計了一個共振器，以衰減發射頻率訊號。 為了達到低雜訊特性與考量覆晶組裝的需求，本論文中的低雜訊放大器所使用的是穩懋半導體GaAs PL15-15 EMR的製程。此為穩懋半導體所提供的新製程，可提供覆晶轉接所需要的銅柱，但相對製程相關資料則較不完整。為了考量到模擬的時效以及準確性，由穩懋提供的電感，電容等量測資料，在電磁模擬軟體中使用薄金屬等效的方式，建立與穩懋量測資料相符合的電磁模擬環境。 基於對低雜訊放大器的要求，在此篇論文中總共介紹了兩種。第一種低雜訊放大器，為了要選擇左旋極化及右旋極化的訊號，在兩個相同的低雜訊放大器輸出端放置了一個單刀雙擲的切換器來選擇。因為良好的輸入返回損耗以及相對低的雜訊指數無法同時得到，所以我們設計了兩種版本。由於此電路採用一新製程，我們亦設計了一系列的測試電路，包括單個電容，電感與TRL校正電路來檢查被動元件是否與穩懋所提供的量測資料貼近。我們也下了不同尺寸的電晶體，以及由三級的低雜訊放大器中分出來的單級低雜訊放大級來驗證電路的特性。 由於三級低雜訊放大器在量測以及模擬上有差距，我們藉由測試電路的量測資料，以及匹配網路的電磁模擬資料，做除錯的動作。最後發現，一開始採用的薄金屬等效模擬方法，並不貼合事實。而地的完整性與否，也會在電路的特性上有相當大差異。藉由除錯過程將此一新製程的模擬環境建立。 第二種低雜訊放大器由周正峯根據第一種低雜訊放大器的的經驗，在電路佈局時儘可能地減少了電感間的耦合現象。而為了節省低雜訊放大器的面積，重新設計了電路架構。在電路中使用兩個一級低雜訊放大器在輸入端，並且以關閉其中一個第一級電晶體的方式，來選擇想要的路徑的訊號。為了減輕製程變異的影響，我們也設計了偏壓電路，可將CMOS端的電流源經由偏壓電路產生低雜訊放大器所需要的偏壓值。在驗證偏壓電路上各個節點的直流偏壓情況後，我們得到量測與模擬相似的結果。This thesis describes the design of the Ka-band low noise amplifier (LNA) which is applied to the front end of a phase array system for satellite communications. The operation frequencies of the receiver and transmitter are 19.2 GHz and 29 GHz, respectively. In order to select the receiving left-handed or right-handed signal, the LNA design should include the function of switching signal path. According to the system requirements, the center frequency for LNA is 19.2 GHz with a bandwidth of 3 GHz, and the gain and the noise figure should be better than 18 dB and 1.3 dB, respectively. The DC power consumption is less than 21 mW. Because the leakage signal from the output of the PAs may degrade the linearity of LNAs, a 29-GHz resonator is added for the LNA to attenuate the leakage signal from transmitter. For low noise characteristics and flip-chip assembling consideration, 0.15-um GaAs pHEMT process with copper pillar for flip-chip connection, WIN PL15-15 EMR, is selected for this design. Because it is a new process, the data offered from foundry is not complete. To speed up the simulation with reasonable accuracy, the metal without thickness in EM simulation software is used to simulate the passive components, and the simulation results are compared with the measurement data provided by WIN. There are two versions of the LNA design in this thesis. For the first version, in order to select the signal from left-handed or right-handed circular polarization port, a single-pole-double-throw (SPDT) switch is used at the output of two identical LNAs. Since excellent input return loss and very low noise figure cannot be achieved simultaneously, another version of LNA is designed for better input return loss. Because we use a new process to design LNA, a set of test kits including a capacitor, an inductor and TRL calibration kits are designed to check the characteristics of passive components. Besides, we are also taped-out different size transistors used in the LNA and switch, and one-stage amplifier cut from 3-stage LNA is also taped-out to verify the circuit characteristics. Due to the difference between the measurement and simulation results, the debug work is implemented according to the measurement results of the test kits. We found that the metal without thickness in EM simulation software is not good enough, and the completeness of the ground plane also has significant effect to the circuit characteristics. Therefore the EM simulation environment is corrected, and the circuits are re-simulated using the new EM simulation environment. For the second version LNA, in order to save the area, the switch in output of LNA is removed. Instead, two 1-stage LNAs are used for the input stage, and turn off one of the LNA to select left-handed or right-handed circular polarization. To choose the polarized signal which is desired and minimize the effect of the process variation, a bias circuit that could switch path by outer signals and controlled by a reference current is designed on GaAs chip. This bias circuit could get more steady bias in gate terminal of transistor in simulation. When we verify the DC bias conditions in the bias circuit on chip, we find that the measurement result is close to simulation result