A Pattern-Aware Write Strategy for Hybrid PCM Storage Devices

中文摘要 電腦架構演變至今,有許許多多的候選者被期待於取代目前的硬盤儲存裝置,在這些候選者當中相變化記憶體是非常備受期待的次世代儲存裝置,由於他有著高密度和極低的使用延遲所以非常適合作為現代架構下的儲存裝置。但是相變化記憶體的高耗能是一個非常嚴重的致命傷,而目前的寫回策略中並大多都是以減少頁缺失次數為目標,並沒有以最佳化儲存系統耗能為出發,另外相變化記憶體的耗能和他所存的資料特徵有關,因此本文提出一個考量儲存資料特徵並且以減少耗能為目標的寫回策略。 關鍵字: 相變化記憶體,儲存裝置系統, 耗能最小化, 寫回策略, 特徵感知ABSTRACT Phase change memory (PCM) is a potential candidate on the storage applications due to its nanosecond-level access latency and byte-addressability. In addition, with the help of multiple-level-per- cell (MLC) technology, PCM could provide comparable capacity to flash memory. However, adopting MLC PCM needs much larger power consumption than SLC PCM. Thus, in this paper, we exploit a SLC/MLC hybrid memory architecture with the proposed pattern-aware write back policy to minimize the energy consumption on the storage devices In addition, we also propose a counter buffer design to reduce the cost on manipulating data structures, and meanwhile, we design a data migration mechanism to migrate data to MLC PCM when the space of SLC PCM is exhausted. We conducted the experiments on the well-known benchmarks and for which the results are encourage