A 25-Gbps Dual-Loop Clock and Data Recovery Circuit with Enhanced Data Rate Deviation Tolerance

時脈資料回復電路在有線通訊系統中扮演一個重要的角色，是一位於接收端的重要子電路，它能夠將經過長距離傳輸後具有雜訊和抖動的資料回復成乾淨的資料以利下一級電路使用。在電路架構實踐上有許多選擇，如以鎖相迴路為基礎的系統、以相位內插器為基礎的系統及以超頻取樣為基礎的系統等。 在本論文所提出一25-Gb/s具高頻率誤差容忍度之雙迴圈時脈資料回復電路。此電路裡面包含了兩個路徑，其中之一是比例路徑，另外一個是積分路徑。比例路徑和傳統以相位內插器為基礎的系統一致，可以對及時的抖動迅速產生反應。積分路徑則是透過長期累積時脈和資料的相對關係，從而萃取出資料的頻率資訊，透過除小數鎖相迴路來改變回復時脈的頻率，進而達到擴大資料率誤差容忍度的目的。 量測的結果，在0.9伏特電源供應下消耗152毫瓦，在鎖相迴路鎖定的情況下，相位雜訊在頻率偏差10 MHz為的地方為-100 dBc/Hz。調整頻率震盪器的電容陣列的情況下，鎖相迴路的鎖定範圍可以將頻率震盪器鎖定在23.7 GHz至27.3 GHz。Clock and data recovery (CDR) circuit plays an important role in wireline communication, which can recover data with less jitter and filter channel interference. There’re a few common structures in CDR, phase-locked loop base CDR, phase interpolator based CDR and oversampling CDR. The thesis proposed a 25-Gb/s dual-loop CDR circuit with enhanced data rate deviation tolerance. The proposed CDR circuit contains two feedback paths, one is proportional path, another one is integral path. Proportional path is identical to the traditional phase interpolator based CDR, which is capable of tracking to instant jitter quickly. The integral path is realized by long term accumulation of the information between clock data, which can extract the frequency information of data, and change the nominal VCO oscillation frequency by adjusting the fractional N phase-locked loop. These two paths together improve the data rate deviation tolerance of CDR. The measurement results show that the circuit consumes 152 mW under 0.9 V VDD supply. VCO’s phase noise is -100 dBc/Hz at 100-MHz. The phase-locked loop can lock VCO’s oscillation frequency from 23.7 GHz to 27.3 GHz.Chapter 1 Introduction 1 1.1 Introduction to Optical Communication 1 1.2 Introduction to Clock and Data Recovery Circuit 2 1.3 Thesis Overview 3 Chapter 2 Basics of Clock and Data Recovery Circuits 5 2.1 Basics of a CDR Circuit 5 2.2 Frequency Detection 6 2.3 Phase Detection 7 2.3.1 Hogge Phase Detector 7 2.3.2 Alexander Phase Detector 8 2.3.3 Comparison 10 2.4 Jitter in CDR Circuits 10 2.4.1 Jitter Transfer Function 12 2.4.2 Jitter Peaking 12 2.4.3 Jitter Generation 13 2.4.4 Jitter Tolerance 14 2.5 Architectures of CDR Circuits 15 2.5.1 PLL-based CDR 15 2.5.2 Phase Interpolator Based CDR 16 2.5.3 Blind Oversampling CDR 17 Chapter 3 A 25-Gb/s Dual-Loop Clock and Data Recovery Circuit with Increased Data Rate Tolerance in 40nm Process 19 3.1 Introduction 19 3.2 System Architecture 20 3.3 Proportional Path 23 3.4 Integral Path 25 3.5 Behavior Simulation 27 Chapter 4 Implementation of a 25-Gb/s Dual-Loop Clock and Data Recovery Circuit 33 4.1 Introduction 33 4.2 Voltage Controlled Oscillator Design 34 4.3 High-Speed Divider 36 4.4 Phase-lock Loop Design 36 4.5 Half Rate Sampler 39 4.6 Phase Interpolator 40 4.7 CDR 43 Chapter 5 Measurement Result 45 5.1 Layout and Chip Photo 45 5.2 Measurement setting 45 5.3 Printed Circuit Boards Design 46 5.4 Integer N PLL Measurement Result 46 Chapter 6 Conclusions and Future Works 53 6.1 Conclusions 53 6.2 Future Works 53 Appendix 55 References 5