Investigation of Gate Dielectrics and Carbon Interstitials on 4H-SiC MOS Capacitors

本論文中，我們研究各種氧化層於碳化矽金氧半電容上的表現，其中包含氧化鋁、氧化鉿、二氧化矽，首先、我們使用高介質氧化層沉積於碳化矽上，其電容電壓圖遲滯現象相當小，定電壓測試下無缺陷捕捉，但是，漏電流大，且於其變頻電容電壓圖中發現了顯著的頻率分散現象，隨著量測頻率的上升，電容值下降，我們對此現象進行了分析與討論，提出了等效電路模型，隨著偏壓改變邊界電阻(Rbt)，此模擬非常符合實驗數據。我們以熱氧化於碳化矽上生長二氧化矽，發現了隨著氧化層的厚度增厚(=15.5奈米)，多餘的未氧化的碳原子，會嵌於碳化矽中，其位置接近於二氧化矽介面，且會吸引電子，本論文以X射線與歐傑光譜儀首度證實其存在，相對地，7.5奈米厚的二氧化矽具有理想的電性與化學組成，並無碳積聚。同時、對於氧化鉿/二氧化矽/碳化矽電容做電性量測，解釋碳積聚對電容電壓圖的影響，分析其穩定度，最後、我們使用X射線光譜分析，以逐層分析，細部的描繪了二氧化矽/碳化矽之能帶圖，發現了薄的二氧化矽具有理想的能帶圖，隨著厚度增厚，二氧化矽的能隙與傳導帶隙會下降，從以上的實驗得知，於碳化矽上生長閘極氧化層，大約7.5奈米厚的二氧化矽為首選，具備良好電性且不存在碳積聚。In this dissertation, we have investigated different gate dielectrics on 4H-SiC, such as Al2O3, HfO2, and SiO2. At first, high-κ dielectric was deposited on SiC for MOS capacitors. The hysteresis of capacitance-voltage (C-V) curves is small and charge trapping under constant field stress is negligible. However, the leakage current is large, and the C-V shows significant C-V frequency dispersion. When the frequency increases, the measured capacitances shift downward because of border traps effect. We first proposed an equivalent circuit model including border trap effect to explain the C-V frequency dispersion on SiC. With suitable Rbt at different biases, this simulation can fit the experimental data successfully.Second, the SiO2 with different thicknesses are grown on 4H-SiC by thermal oxidation. By X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES) analysis, we first detected the C interstitials or clusters in SiC. The thick SiO2 (15.5nm) produced C interstitials in SiC.The C interstitials would trap electron during the constant field stress test. On the other hand, the thin SiO2 (7.5nm) has ideal electrical property and chemical composition, and the SiC substrate does not contain excess C in it. Moreover, we investigated different thickness of SiO2 using XPS analysis. We first depicted SiO2/4H-SiC energy band alignment of the different SiO2 thicknesses layer by layer. The Band gap (EG) and conduction band offset ( ) of SiO2 are reduced when grow thicker SiO2. The surface SiO2 layer is more perfect than the bottom layer. Nevertheless, from the XPS depth profile, both thin and thick SiO2 did not contain the silicon oxycarbides (SiCxOy) in it. From experimental result of study, the 7.5 nm SiO2is the best dielectric for SiC, which has ideal band structure and no excess C contamination.誌謝 i 摘要 ii Abstract iii Contents iv Figure Captions vi Table Captions ix Chapter 1 Introduction 1 1-1 SiC Substrates and Oxidation Process 1 1-2 High- Gate Dielectrics 5 1-3 Combined High-low Frequency Method for Determining Density of Interface Traps (Dit) 8 1.4 X-ray Photoelectron Spectroscopy (XPS) 9 Chapter 2 Frequency Dispersion of Metal-Al2O3-SiC Capacitors Containing Border Traps Effect 21 2-1 Introduction 22 2-2 The Fabrication Processes of Al/Al2O3/4H-SiC Capacitors 25 2-3 Electrical Property of SiC Capacitors with Thin Al2O3 Gate Dielectric 27 2-4 Modeling of Border Traps Effects on SiC Capacitor 30 2-5 Summary 37 Chapter 3 Detection of Thickness-dependent Excess Carbon in HfO2/SiO2/4H-SiC Structure 49 3-1 Introduction 50 3-2 Experimental 51 3-3 Results and discussion 53 3-3-1 C-V Characteristics and HRTEM Images 53 3-3-2 CarbonInterstitials in SiC 55 3-4 Summary 58 Chapter 4 Improvement of Electrical Performance of HfO2/SiO2/4H-SiC Structure with Thin SiO2 63 4-1 Introduction 64 4-2 Experimental 67 4-3 Results and discussion 69 4-3-1 Electrical Properties and Chemical Compositions of the Capacitors 69 4-3-2 Constant Stress Reliability of the Capacitors 75 4-4 Summary 78 Chapter 5 Energy-band Alignment of SiO2on 4H-SiC Measured Layer by Layer 89 5-1 Introduction 89 5-2 Experimental 91 5-3 Results and Discussion 93 5-4 Summary 97 Chapter 6 Conclusions 104 6-1 Conclusions 104 6-2 Suggestions for Future Work 106 References 10