Time-mode Sigma-Delta Interface Circuit for Capacitive Sensors

此論文中闡述了電容式感測器介面電路的設計與實作。實作出來的電路於一般取樣頻率下能達到費法拉等級的解析度，能用在量測受到形變的感測器的電容值變化量。由於待測物電容值與輸出的數位碼呈線性的對應關係，在計算未知電容值時可以利用簡單的內插法得到。透過使用台積電標準0.18微米互補式金氧半導體製程，一共有兩個介面電路實作出來並且藉由量測得到功能的驗證。首先，我們先介紹時間模態來做為製程間可攜式的解決方法。三角積分調變器則用來達成高解析度以及輸入與輸出的線性關係。此電路為了避免使用傳統的類比組成區塊，因此只包含了充電泵及時間模態的三角積分調變器。接著，我們採用一個二位元的架構以及額外的省電技巧藉以達到與先前相同的解析度表現但同時間降低了一半的功耗。由於晶片的輸出形式為數位，因此資料可以很簡易的由邏輯分析儀進行蒐集，接著在電腦上利用MATLAB軟體進行後續處理。兩顆晶片的面積皆為0.68*0.68平方毫米。工作電壓操作在1.2伏特的情況下，晶片的功耗分別為817微瓦及360微瓦，有效位元數(ENOB)分別為8.8及9.07，而品質因數(FoM)分別為114.5皮焦耳和41.7皮焦耳。This thesis illustrates the design and implementation of interface circuits for capacitive sensors. The interface circuits perform femto farad resolution at typical sampling rate, which is designed for measuring the change of capacitance under physical change. With linear corresponding relationship between capacitance and output digital code, the interpolation is available in capacitance calculation. By using a standard TSMC 0.18-μm CMOS process, there are two circuits implemented and the functions are verified in measurement results. Firstly, time-mode approach is introduced to provide a solution suitable for process migration. A sigma-delta modulator is employed to achieve high resolution and the relationship between input and output digital code is linear. The proposed sensor interface is simply composed of a charge pump and a time-mode sigma-delta modulator to reduce the need for traditional analog building blocks as much as possible. Secondly, the multi-bit architecture and additional power-saving techniques are applied to maintain overall performance while reducing the power consumption by half. With the digital output generated form the fabricated chip, the raw data can be easily collected with a logic analyzer and then processed directly with MATLAB on a computer. The chip areas are both 0.68*0.68 mm2. Operated at a 1.2-V supply voltage, the fabricated circuits consume average power of 817 μW and 360 μW and achieve an effective number of bits (ENOB) of 8.8 and 9.07 and figure-of-merit (FoM) of 114.5 pJ/step and 41.7 pJ/step, respectively.摘要 I Abstract III Table of Contents V List of Figures VIII List of Tables XI Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis overview 3 Chapter 2 Background 5 2.1 An overview of sensors 5 2.2 Parameters of sensing interface circuits 8 2.2.1 Sensitivity 8 2.2.2 Resolution 9 2.2.3 Dynamic range 9 2.2.4 Sampling rate and conversion time 10 2.2.5 Accuracy 10 2.2.6 Figure-of-merit 11 2.3 Varied Approaches of the Interface Circuits 11 2.3.1 AC voltage amplification 11 2.2.2 Transimpedance amplification 12 2.2.3 Charge amplification 13 2.2.4 Time-mode approaches 13 2.4 Time-mode signal processing 14 2.4.1 Voltage-to-time integrator 15 2.4.2 Digital-to-time converter 16 2.4.3 Time-to-digital converter 17 2.5 Oversampling and sigma-delta modulator 20 2.6 Design methodology 20 Chapter 3 A Time-mode Sigma-Delta Interface Circuit for Capacitive Sensors 23 3.1 Introduction 24 3.2 Proposed architecture 25 3.3 Circuit implementation 26 3.3.1 Capacitance-to-time (C-to-T) converter 26 3.3.2 Time-to-time integrator 27 3.3.3 1-bit quantizer 35 3.3.4 1-bit digital-to-time converter (DTC) 36 3.3.5 Resembling device under test 37 3.4 Design guideline 39 3.5 Discussion of non-idealities 40 3.6 Experimental results 43 3.7 Conclusion 47 Chapter 4 A Multi-bit Time-mode Sigma-Delta Interface Circuit for Capacitive Sensors 49 4.1 Introduction 50 4.2 Proposed Architecture 51 4.3 Circuit implementation 52 4.3.1 Capacitance-to-time (C-to-T) converter 52 4.3.2 Time-to-time integrator 54 4.3.3 2-bit quantizer 55 4.3.4 2-bit digital-to-time converter (DTC) 59 4.4 Experimental results 60 4.5 Conclusion 64 Chapter 5 Conclusion 65 Bibliography 6