High Speed AC Coupled Interconnection Systems and PI/SI Effects on I/O Circuits with Decoupling Capacitors

近年為了提升來晶片與晶片通訊速度，一些文獻中提出了利用交流耦合的方式傳遞訊號，其有著低功率消耗和高傳輸頻寬的特色，此種方式稱為交流耦合連結，本文在0.18μm CMOS製程下提出可操作在10Gb/s，功率消耗為40mW的脈衝接收器和實做出可操作6Gb/s、功率消耗為11mW的脈衝發送器，其中脈衝接收器運用了電感式翹起和三共振網路改善其操作速度。 而在90nm CMOS製程下提出了一高速低功低面積的交流耦合接收器，其中採用了主動式翹起改善操作速度，交流耦合接收器可操作在13.5Gb/s並且只有5.5mW的功率消耗。 本文也針對界面電路的電源與訊號完整性做探討，在晶片安排了數組可工作在3.2Gb/s的驅動器和去耦合電容，藉由改變發送器工作組數和去耦合電容值，探討電源完整性，另外文中也觀察發送器在不同情況下的輸出眼圖表現，以討論訊號完整性的議題。In recent years, for enhancing the speed of chip-to-chip communication, some papers propose a signaling method which transmits data using AC coupled technique. It features low power consumption and high communication bandwidth, and the system is called AC coupled interconnection. We propose a pulse receiver which is fabricated with 0.18μm CMOS process. The circuit can operate at 10Gb/s and the power consumption is 40mW. Inductive peaking and reversed tripled-resonance network(RTRN) technique are adopted to enhance the bandwidth of the receiver. In this thesis, we also propose an AC coupled receiver which is high speed, low power, but with small chip area with 90nm CMOS process. Active peaking technique is applied to improve the operation speed of the AC coupled receiver, which can work at 13.5Gb/s and only consume 5.5mW. In addition, we discuss the impact of power integrity and signal integrity for interface circuits. A test chip with multiple transmitters operating at 3.2Gb/s and on-chip decoupling capacitors is implemented. By changing the number of inactive transmitters and capacitors, power integrity issue is discussed. Finally, we observe the eye diagrams of the transmitter in different conditions and assess the issue of signal integrity