A Millimeter-Wave Power Amplifier and A Phase-Locked Loop for the W-Band Application

W頻段坐落於75至110 GHz內。此頻段可提供毫米波雷達研究、衛星通訊與軍用雷達鎖定與追蹤等應用。其中近年來76~77 GHz此頻率範圍已經指定給長距離車用雷達使用。因系統嚴苛的規格與要求，目前此雷達系統主要還是以GaAs製程實現。然而隨著CMOS技術的突破，車用雷達系統將可採用CMOS技術來製作，如此將可實現低成本之車用雷達系統。但CMOS技術具有其先天上的缺陷，諸如低電源與崩潰電壓、低增益效能與高損耗被動元件等缺點，將使得以CMOS實現高效能的車用雷達電路為一非常困難的課題。有鑑於此，本論文將提出電路技巧減緩此些製程缺點所造成的障礙，同時並以實際晶片之量測結果加以驗證。 本論文第二章探討77 GHz 功率放大器設計，其中此電路採用短路殘段架構與變壓器形式的功率相加器等技巧來減緩信號損耗與增進輸出功率。量測結果顯示此放大器操作於1.2 V下，可達到 9.9 dB的小訊號增益、11.2 dBm 的P1dB、13.2 dBm的Psat與10.4 %的PAE。此電路驗證CMOS技術確實可實現高功率輸出之毫米波放大器且其效能可與SiGe技術之電路匹敵。 第三章則是提出一個寬鎖定範圍的注入式鎖定除頻器。此電路採用65奈米CMOS技術實現並使用直接多點注入技巧來拓增鎖定範圍，故此電路架構解決傳統除三電路其狹窄鎖定範圍的問題。經由實際量測，此電路於不採用額外的調諧機制下具有9.4 GHz的鎖定範圍，並僅消耗2.8 mW。 最後於第四章中將呈現可應用於W頻帶的低功率鎖相迴路。此鎖相迴路將第三章所提出的除三電路整合至迴路中，且其壓控振盪器採用分佈式儲能槽技巧減輕變容器其低品質因數的影響並提高操作速度，將可不需額外的緩衝器來驅動第一級除頻器。此鎖相迴路若不將測試緩衝器納入功率計算下，僅僅消耗17 mW。故適當地選擇除頻器的架構，毫米波時脈產生器確實可以達到低功率的效能。The W-band lies in the frequency bands from 75 to 110 GHz. This band is used for millimeter-wave radar research, satellite communications, military radar targeting and tracking applications. Especially, the frequency band from 76 to 77 GHz has been allocated for long range automotive radars in recent years. Owing to the severe specifications and requirements, many critical circuits in the automotive radar system are mainly fabricated by GaAs technologies. However, with the continuous advance of the CMOS process, the automotive radar can be realized by the CMOS technology to demonstrate the possibility of the low cost transceiver implementation. Nonetheless, the CMOS technology possesses some inherent drawbacks, which are the low supply voltage, the low breakdown voltage, the low gain and the large loss of on-chip passive components, so it is difficult to realize the high performance CMOS circuits for the automotive radar application. This thesis presents the circuit techniques to alleviate those bottlenecks and also provide the experimental results to verify the functionality. In Chapter 2, the short stub topology and the transformer-based power combiner are employed by the 77 GHz power amplifier to reduce the signal loss and improve the output saturation power respectively. The measured results reveal that this power amplifier achieves a small signal gain of 9.9 dB, a 1 dB compressed output power of 11.2 dBm, a peak power-added efficiency of 10.4% and a saturated output power of 13.2 dBm at 77 GHz under a 1.2 V supply. This work has demonstrated that CMOS technology is suitable for the power amplifier at high output power application such as 77 GHz automotive radar system. Chapter 3 deals with the proposed wide-locking range divide-by-three injection locked frequency divider. This divider is realized in general purpose 65nm CMOS technology. The proposed divider employs the direct multiple-injection technique to enhance the locking range, which solves the narrow locking range problem among conventional divide-by-three injection locked frequency divider. The circuit has a measured locking range from 75.9 to 85.3 GHz without tuning mechanism, while only drawing 2.8 mA from a 1 V supply. In Chapter 4, the low power W-band PLL is presented. This PLL is composed of the proposed divide-by-three frequency divider, which is mentioned in Chapter 3, and the VCO which adopts the distributed-LC tank to mitigate the effect of the low Q factor of varactors and to drive the heavy loading without buffers under the same oscillation frequency. This PLL only dissipates 17 mW excluding testing buffers. Thus this PLL reveals the low power CMOS millimeter-wave clock generator can be achieved by virtue of the high division frequency divider and the proper divider selection