The Analysis of Microlithography Image Simulation and Sub Resolution Assist Feature Combining with HSMO

光學微顯影成像技術(Optical micro-lithography image technology)是目前半導體製造中關鍵的一步。隨著超大型積體電路(VLSI, very-large-scale integrated-circuit)製程技術的演進，元件的特徵尺寸(feature size)已小於現今所使用的曝光光源波長，使得成像結果因光的繞射效應明顯地偏離了原本的設計圖樣(design pattern)。因此，各種採用有效技巧與演算法的解析度增強技術(RET, resolution enhancement technology)廣泛地被提出，以期能使成像結果貼近原本的設計圖樣。眾多代表性的技術如偏軸照明(OAI, off-axis illumination)、相移光罩(PSM, phase shift mask)、光學鄰近修正術(OPC, optical proximity correction)等，均有助於成像結果的改善。 於本論文中，我們考慮結合亞解析度輔助圖形(SRAF, sub-resolution assist feature)以及階層式光源光罩最佳化技術(HSMO, hierarchical source mask optimization)。先藉由添加亞解析度輔助圖形的方式來提高設計圖樣的焦深(depth of focus)，接著再對於光源以及光罩作最佳化，以期能抵消製程的作用而得到原本的電路設計。 然而，在使用解析度增強技術之前，我們必須先確保我們的光阻內成像模擬的正確性。因此，我們考慮完整介紹建立在平面波分解上的光阻內成像模擬，並且將我們程式的成像模擬結果對照Sentaurus Lithography的成像模擬結果，以方便確認我們程式模擬結果的正確性。 此外，以現在元件數以百萬計的電路設計，若以傳統的直接摺積方式去得到成像結果，這將會需要非常大量的時間以及空間。在此論文中，我們將使用阿貝主成份分析(Abbe-PCA, Abbe principal component analysis)對過程中產生的摺積成像核心(convolution image kernel)進行快速壓縮，並利用摺積查表(convolution lookup table)加速最佳化過程中的目標函數(object cost function)的計算。 於本論文中，我們將使用成像強度誤差(IIE, image intensity error)作為我們的目標函數。經過最佳化以後的模擬結果將會比原始成像模擬結果在目標函數值上改善了67.46%，模擬結果不僅更接近原本設計的圖樣並且在對於失焦(defocus)的容錯率上也提升了。Optical micro-lithography technology simulation is a critical step in semiconductor manufacturing. As the VLSI manufacture technology develops, the feature size of micro-electronic devices shrinks smaller than the wavelength of exposure light source in modern microlithography. Consequently, the image quality and resolution on the wafer are getting worse owing to diffraction effect. Therefore, lots of resolution enhancement technologies (RETs) with remarkable skills and algorithms are so far widely proposed to minimize the difference between design pattern and image result. Conventional RETs such as off-axis illumination (OAI), phase shift mask (PSM), and optical proximity correction (OPC) are in favor of improving the printing quality. In this thesis, we consider a method which combines sub resolution assist features (SRAF) and hierarchical source mask optimization (HSMO). Firstly, we add sub resolution assist features for improving depth of focus, and then using the hierarchical source mask optimization for finer image quality. However, we must ensure the correctness of our vector resist image simulation before using resolution enhancement technology. Thus, we’ll completely introduce the optical lithography image system, and compare the result of our simulation to the result of Sentaurus Lithography from Synopsys© for accuracy. Besides, there are millions of devices having to deal with in the nowadays state-of-art, it will take lots of time and space to get the final image result. In this work, we utilize the principal component analysis on Abbe’s image formulation (Abbe-PCA) for high speed kernel compaction on the convolution image kernel, and then the convolution lookup table is used in order to accelerate object cost function evaluation, which usually takes a valuable time consuming to get the full image simulation. In this thesis, we use image intensity error as our cost function. The cost function value of optimized simulation result is 67.46% better than original one, and the optimized result is not only more similar to the original design pattern but also providing finer tolerance of defocus