PI/SI Effects on SDRAM I/O Interface Circuits with Voltage-mode and Current-mode Transmissions

近年來，晶片與晶片通訊速度的提升，造就了整體系統的速度也相對的提升，因此在高速系統下，其雜訊干擾已是不可忽略，本文將對介面電路的電源與訊號完整性做一系列的探討。本論文闡述兩個介面電路，分別為電壓(VMOCD)與電流(CMOCD)的I/O 介面傳輸，都是操作在 1.1 伏特及傳輸速度為3.2Gbps 的DDR4 I/O 介面傳輸電路，並以聯電90-nm CMOS 製程製作。在晶片中均包含了傳輸器以及接收器電路，也加入了多組的去耦合電容以及額外的傳輸器電路，並觀察在各種不同的情況下的眼圖變化，來探討電源與訊號完整性的議題。 由於在本文中有探討兩種不同的I/O 介面電路，在各自做完模擬與量測後，再互相做比較，由結果得知電流傳輸模式對雜訊干擾的抑制效果比較好，其功率消耗也相對的較低。根據我們發現了模擬與實際測試板的量測的差異性，得知在高速電路下封裝及電路板模型建立的重要性，因此我們也加入了模型的建立來進行模擬，並在最後呈現我們的模擬及量測的結果。In recent years, the speed of chip-to-chip communication is upgrading which makes the speed of whole system to be faster. Hence, under high speed system, its noise coupling would not be ignored. This paper will propose a series of discussion for the signal integrity and power integrity of I/O interface circuits. This thesis presents two I/O transmission interface circuits which are voltage mode OCD (VMOCD) and current mode OCD (CMOCD). They are all operated at 1.1V, 3.2Gbps data rates and produced by standard UMC 90-nm CMOS process. And the transmitter and receiver circuits are included in the chip. To discuss the signal integrity and power integrity issues, many decoupling capacitors and extra transmitter circuits are added then observed the eye-diagram variation in each kind of different case. In this thesis, discussion about two I/O interface circuits, and the simulation and measurement each other, then compare their results. The current mode OCD (CMOCD) has more noise resistance than the voltage mode OCD (VMOCD). And its power consumption is also lower. According to the difference between simulation and real test board measurement, the importance of model establishment for package and test board under high speed circuit are known. Therefore, the model establishment is added into the simulation. Finally, the results of the simulation and measurement are presented