A Soft Error Tolerant D Flip-Flop Design

In recent years, soft error problem is an important reliability issue. Soft errors cause a severe problem especially for memories or flip-flops. When various particles strike on the device, a transient pulse occurs. If this transient pulse flips the data stored in the memory or the flip-flop, a soft error occurs. Soft error can be classified into Single Event Transient (SET), which occurs in the combinational logic; and Single Event Upset (SEU), which occurs in memory elements like flip-flop. Researches propose many designs to tolerate soft error in the flip-flop. However, these designs usually have large performance penalty and occupy large area overhead, so that they are not useful in simple circuits. In this thesis, we propose a new flip-flop：Soft Error Tolerant D Flip-Flop (SETDFF) to tolerate SEU, and has some SET tolerate ability. This SETDFF cell achieves the same performance with general D flip-flop and occupies less area overhead. Our SETDFF design use C-element to tolerate soft error: two inputs of the C-element come from different signals with the same value. When SEU or SET occurs, inputs of the C-element disagree with each other, and C-element rejects the transient pulse and blocks the soft error. Experiment results show that, compared with the BISER architecture proposed by other paper, our SETDFF design achieves similar SEU tolerate ability and better SET tolerate ability. At the same time, our design has 13% and 70% less performance and area overhead penalty. In our SETDFF design, SER has relationship with input arrival time. Therefore, we propose Soft Error Tolerant Time (SETT). The concept is that as long as the data arrives in a time period, we guarantee the SER under the threshold, and this time period is SETT. Circuit designers can achieve the balance between performance and SER according to this information