Research on Linearization Technique for CMOS Power Amplifier

這篇論文將提出一個可以使用在毫米波頻段的改良式線性器，具有改善互補式金氧半導體功率放大器的功能。在此之前所提出的線性器是使用在40 GHz，並使用了砷化鎵高電子移動率電晶體製程，展現了良好的特性。然而，同樣的架構卻難以在60 GHz頻段有效的移植到互補式金氧半導體製程。因此，我們探討了現性器的詳細運作情形，並提出以相位延遲線來改善普通線性器的改進。另外，我們提出了一個偏壓優化的方法，可以保證針對特定功率放大器可以找到最適合的線性器大小及其控制偏壓。 我們使用90奈米LP互補式金氧半導體來製作一個在60 GHz的功率放大器，並且完全的以提升1 dB衰減點為目標，來做出優化。量測的結果，功率放大器在增益1 dB衰減點呈現了高達14 %的功率附加效率。並且，其還具有15 dB的小訊號增益、13.7 dBm的增益1 dB衰減輸出功率以及15.4 dBm的飽和輸出功率。這是我們所知，在所有發表過的電路中，使用互補式金氧半導體製程在增益1 dB衰減點有最高功率附加效率的60 GHz功率放大器。In this dissertation, a modified cold-FET pre-distortion linearizer is proposed to improve the linearity of the millimeter-wave CMOS power amplifiers. The previous reported cold-FET linearizer as applied to a 40 GHz power amplifier with a low-loss built-in linearizer in GaAs HEMT technology [6]. However, the effect of the linearizer is not good enough when we try to transplant the technique to 60 GHz using CMOS technology. Therefore, we investigate the operation detail of the linearizer and propose a modified linearizer by adding a delay line. Besides, a bias optimization method that can effectively guarantee the linearity of specific cascode device for power amplifier application is also presented. A 60GHz cascode power amplifier with modified linearizer is then fabricated under 90-nm LP CMOS technology and fully characterized to enhance its linearity which demonstrated by its extremely well OP1dB. The measurement results of the power amplifier show a power-added-efficiency at OP1dB up to 14% while maintaining 15 dB small signal gain, 13.7 dBm OP1dB and 15.4 dBm Psat. It is the highest power-added-efficiency at OP1dB for millimeter-wave CMOS power amplifiers which ever been published